The core of a modern high speed microprocessor system, as shown in FIG. 1, consists of number of subsystems such as the microprocessor (CPU 11), secondary cache controller 12 and the secondary cache memory 13. The communication between the subsystems is performed over the CPU bus 14. Highly integrated modern VLSI processes, allows the CPU 11 to include an on chip primary cache 15 and floating point unit (FPU 16). The CPU 11 may generally include additional units that are not essential to the subject matter of this invention and are therefore omitted for clarity from FIG. 1.
Synchronous operation of the various units in the microprocessor system is accomplished by means of the CLK signal. Each unit uses the CLK signal for sequencing the operation of internal sequential logic circuits such as synchronous state machines. Inside CPU 11, the CLK is generated by the clock generator circuit (CLKGEN) 17. In the past, a double frequency (2X) clock signal, CLK2, was used as a main system reference clock. The CLK2 reference signal comprised a series of pulse waveforms with twice the frequency of the CLK signal (.sup.f CLK2=2.cndot..sup.f CLK). FIG. 2 shows a typical prior art implementation of the CLKGEN circuit 17. The frequency of external CLK2 signal is divided by two by D-type flip-flop (TFF) 18 with its Q# output connected to its D input and buffered by a clock driver (CLKDRV) 19, creating the internal CLK signal with 50% duty-cycle, regardless of the duty-cycle of the external CLK2 signal.
Recent advances in VLSI technology allow internal CPU operation at clock rates of up to 200 MHz which elevates the 2X clock frequency to 400 MHz respectively. At these frequencies, designing the system distribution of the 2X clock is very complex, expensive and requires substantial skill in high frequency analog techniques. Moreover, at frequencies of 200 MHz, the 2 to 3 ns delay of the on-chip CLK driver may constitute a significant delay of more than 50% of the CLK period. These delays preclude the use of traditional means for CLK generation in modern microprocessors. An additional limitation that results from the use of a high frequency microprocessor CLK signal is due to the limited high frequency response of external bus 14. This high frequency loss results because the microprocessor system mechanical dimensions (specifically the length of interconnect traces), are comparable to the wavelength of the CLK signal. As a result, the interconnect lines must be treated as transmission lines rather than lumped capacitors, thereby significantly complicating microprocessor system board design.
For CLK frequencies up to approximately 66 MHz, a possible way to solve the problem is to use the lower frequency (1X) CLK signal as the system clock instead of the double frequency (2X) (CLK2) signal. However, because of the need to have a 50% duty-cycle internal CLK signal with zero skew relative to the external clock signal, it is necessary to eliminate the delay of the internal clock driver 19. (To eliminate the confusion between the internal and the external clock signals, the external clock will be referred to as CLKTTL and the internal clock as CLK.) Patent application Ser. No. 07/890,038 filed May 28, 1992, now issued U.S. Pat. No. 5,317,202 entitled: "Delay Line Loop for 1X On-Chip Clock Generation with Zero Skew and 50% Duty Cycle," provides an adequate solution for operation below 66 MHz.
For frequencies of 66 MHz and above, it becomes more practical to operate the microprocessor system with the CLKTTL frequency even lower than the internal CLK frequency. For example, one should consider operating at an internal CLK frequency of 66 MHz while using an external CLKTTL frequency of 33 MHz. This mode of operation is referred to as the (1/2)X mode in the rest of this patent application. The use of other submultiple modes are also possible. In general they are referred as (1/N)X modes.
For the 1X or (1/N)X operating modes, one way to generate CLK with a 50% duty-cycle and zero skew between the external CLKTTL and the internal CLK signals is by using a phase-locked-loop (PLL), as shown in the block diagram of FIG. 3(a) and the associated waveforms as shown in FIG. 3(b). The use of a sequential phase-frequency detector (PFD) 20 and Charge-Pump (CP) 21 in the PLL results in zero skew between the REF and FB signals. The OR1 and OR2 gates have equal delays thereby, the respective CLKTTL and CLK rising edges are also aligned with zero skew. CLK frequency multiplication is accomplished by the use of the 1:N frequency divider 26 in the feedback loop of the PLL. The waveforms in FIG. 3(b) show the circuit operation for N=2 or (1/2)X operation mode. The arrangement of the frequency divider 26 together with the OR1 and OR2 gates allows the creation of the CLK signal having a frequency of N times the CLKTTL frequency while keeping the CLK signal and CLKTTL signal rising edges in phase. The 50% duty-cycle is realized by using voltage controlled oscillator (VCO) 23 oscillating at twice the CLK frequency and then dividing its frequency by two using frequency divider network 24 which is similar to divider network TFF 18 of FIG. 2. Further details about charge pump PLLs may be found in Gardner, F., Phaselock Techniques (John Wiley, 1979).
However, implementation of a PLL circuit using a digital VLSI process and operation of a PLL on the same substrate with noisy digital (on-off) circuits such as microprocessors, introduces further complications. The PLL analog circuit performance and reliability is adversely affected by this digital noise. The degree of sensitivity to noise is strongly affected by manufacturing process variations and by operating conditions. On the other hand, the digital parts of the microprocessor system are more robust than the analog parts of the PLL, showing greater immunity to process and environmental variations. Hence, reliable operation of PLL circuit on the same substrate with digital microprocessor, is very difficult to guarantee.
As can be seen from FIG. 3, the PLL's low pass filter (LPF) 22 uses a resistor R2 which is required to assure closed loop stability of the PLL. Unfortunately, modern digital VLSI processes lack the ability to provide reasonably valued resistors unless a well type resistor is used for R2. However, well-type resistors have high parasitic capacitance to the silicon substrate. In digital chips, like a microprocessor, this may lead to the coupling of the substrate noise to the sensitive LPF 22 output node, V.sub.CNTL. Noise on node V.sub.CNTL has a deleterious effect on the operation of the PLL because it directly modulates the phase and frequency of the CLK signal. Hence, the zero skew locking of the PLL may be subjected to significant errors due to the substrate noise coupling.
In addition, it can be shown that the oscillation frequency of the VCO is highly sensitive to the power supply voltage noise. When the digital part of the microprocessor is operating, a very high noise level is generated on the internal power supplies of the chip due to on-off transients which significantly modulates the phase of the CLK signal. Consequently, the zero skew locking of the PLL is very difficult to guarantee due to noisy power supplies. One may suggest a separate set of filtered power supplies, solely for the PLL circuit on the microprocessor chip. However, use of isolated power supplies raises serious electro-static-discharge (ESD) reliability problems in addition to requiring additional filtering components external to the chip.
Therefore, it is undesirable to implement a mass production PLL circuit which must be guaranteed to operate reliably by using a standard digital VLSI process, residing on same substrate with the noisy digital circuits.